Semiconductor device having raised source and drain of differing heights

ABSTRACT

This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of co-pending application Ser. No.12/022,363 filed on Jan. 30, 2008, which claims foreign priority toJapanese patent application No. 2007-021777 filed on Jan. 31, 2007. Theentire content of each of these applications is hereby expresslyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, a fabricationmethod for a semiconductor device, and a semiconductor memory device,wherein non-symmetricalness has been applied to a structure of thesource and the drain portions, in a structure having an MOS(Metal-Oxide-Semiconductor) transistor of a structure wherein a siliconlayer has been grown on the source and the drain regions to be formed ona silicon semiconductor substrate by using silicon selective epitaxialgrowth technology.

2. Description of the Related Art

In recent years, in the main components of computers and electricinstruments, large-scale integrated circuits (below, referred to asLSI), where many MOS transistors and/or resistors are intergraded on onechip have been adopted. In LSI, for example, in elements such as theDRAM (Dynamic Random Access Memory), rapid micronization advances, andwith this, the so-called short channel effect of the MOS transistorbecomes remarkable.

Therefore, as one of the methods for controlling the short channeleffect, a technology is employed in which: an epitaxial silicon layer isformed on a source region and a drain region on the MOS transistor byselective epitaxial growth; and utilizing the epitaxial silicon layer asa region of the source and the drain (cf. Japanese Unexamined PatentApplication, First Publication No. 2005-251776). In addition, in thistechnology, it is also known that the greater the thickness of theepitaxial silicon layer is, the easier it is to control the shortchannel effect.

In addition, a structure is known in which, in the region on asemiconductor substrate sectioned by an element separation dielectricfilm, two MOS transistors are arranged; an elevated source/drainstructure is applied to each MOS transistor; an epitaxial layer isestablished on each of the source and drain regions; and the surfaceposition of the epitaxial layer that functions as these source/drainregions are at positions that are higher than the channel of each MOStransistor (refer to Japanese Unexamined Patent Application, FirstPublication No. 2000-260952).

However, diffusion laminar structure of the source and drain regionsformed on the semiconductor substrate were the same in all of theconventional transistor structures of this type. That is to say, becauseimpurity profiles of the source and drain regions are the same, theelectric field strengths of the source and the drain regions are of thesame structure.

In addition, in order to employ an asymmetric structure in a transistorhaving this kind of conventional structure, there is a method in which:a photolithography process is added; resist patterns is formed foropening only the drain region for example; and impurities are introducedonly into the drain region by an ion implantation.

However, in this case, there are problems in which: the number ofprocesses will increase and thereby increasing the cost; and, when thewidth of the drain is small, the opening of different height resistpatterns become necessary, and thereby causing unstable yield.

Incidentally, the elements such as the above-mentioned DRAM has athree-dimensional structure in which a capacitor structure is arrangedon the MOS transistor, and word wirings and bit wirings are formedbetween the MOS transistor and the capacitor structure in the length andwidth. Therefore, the equal electric fields from the source and thedrain regions will be applied to both of the contact portion between theMOS transistor and the contact portion and the contact portion betweenthe MOS transistor and the capacitor structure. Here, under the presentsituations where micronization of the element such as the DRAM advances,any of the MOS transistor, various wirings such as the bit wiring, andthe capacitor structure are in a situation where they are micronized,and each component is distributed adjacently. Therefore, the capacityremaining in various wirings while performing a refreshing operationwhich is essential for the DRAM operations is increased. This causes aproblem of a signal delay in the refreshing performance.

Therefore, a superior structure having a refreshing performance isdesired in the DRAM where the internal structure is made minute.

The present invention was made in view of the above circumstances, andhas an object of providing a semiconductor device and a fabricationmethod thereof, which can suppress a generation of a hot-carrier andthereby improving the hot-carrier tolerance by applyingnon-symmetricalness into the structure of the source region and thedrain region in a MOS transistor structure where the silicon layer isformed on the source region and the drain region using silicon selectiveepitaxial growth technology.

In addition, the present invention also has an object of providing asemiconductor memory device having superior refreshing performancewithout adding a complicated process.

SUMMARY OF THE INVENTION

The present invention adopted the following means to solve theaforementioned problem.

(1) A semiconductor device including an MOS transistor provided with: agate electrode formed on a semiconductor substrate; a source region nextto one side of the gate electrode; and a drain region next to anotherside of the gate electrode, wherein: an upper end of the source regionand an upper end of the drain region are at positions where are higherthan a top surface of the semiconductor substrate; and the height of theupper end of the source region differs from the height of the upper endof the drain region.

(2) In the semiconductor device according to the above (1), it may bearranged such that, due to the difference in height from the top surfaceof the semiconductor substrate of the upper end of the drain region andthe height from the top surface of the semiconductor substrate of theupper end of the source region, at an end of the gate electrode in thesemiconductor substrate, an electric field strength in the vicinity ofthe source region and an electric field strength in the vicinity of thegate region differ from each other.

(3) In the semiconductor device according to the above (1), it may bearranged such that the width of the drain region and the width of thesource region along a source-drain direction across the gate electrodediffer from each other.

(4) In the semiconductor device according to the above (1), it may bearranged such that, the height from the top surface of the semiconductorsubstrate of the upper end of the drain region is higher than the heightfrom the top surface of the semiconductor substrate of the upper end ofthe source region.

(5) In the semiconductor device according to the above (1), it may bearranged such that, the width of the source region along a source-draindirection across the gate electrode is wider than the width of the drainregion.

(6) In the semiconductor device according to the above (1), it may bearranged such that, a semiconductor substrate surface area in the sourceregion is larger than a semiconductor substrate surface area in thedrain region.

(7) The semiconductor device according to the above (1) may be furtherprovided with a dummy gate electrode, where no voltage is applied, isadjacent to either one of the source region or the drain region.

(8) A semiconductor device provided with: a gate electrode formed on asemiconductor substrate; a source region next to one side of the gateelectrode; a drain region next to another side of the gate electrode; abit wiring connected to the source region; and a capacitor connected tothe drain region, wherein: an upper end of the source region and anupper end of the drain region are at positions where are higher than atop surface of the semiconductor substrate; and the height of the upperend of the source region differs from the height of the upper end of thedrain region.

(9) In the semiconductor device according to the above (8), it may bearranged such that the height from the top surface of the semiconductorsubstrate of the upper end of the drain region is higher than the heightfrom the top surface of the semiconductor substrate of the upper end ofthe source region.

(10) In the semiconductor device according to the above (8), it may bearranged such that the width of the source region along a source-draindirection across the gate electrode is wider than the width of the drainregion.

(11) In the semiconductor device according to the above (8), it may bearranged such that: the gate electrode or a dummy gate electrode towhich no voltage is applied is arranged on both sides of the sourceregion and both sides of the drain region; and the distance between thegate electrodes or between the dummy gate electrodes arranged on theboth sides of the source region is smaller than the distance between thegate electrodes or between the dummy gate electrodes arranged on theboth sides of the drain region.

(12) In the semiconductor device according to the above (8), it may bearranged such that a semiconductor substrate surface area of the sourceregion is larger than a semiconductor substrate surface area of thedrain region.

(13) In the semiconductor device according to the above (8), it may bearranged such that the gate electrode constitutes a word wiring.

(14) A fabrication method for a semiconductor device, including thesteps of: forming a gate electrode on a semiconductor substrate; andforming a silicon layer on a top surface of the semiconductor substratein a source region next to one side of the gate electrode, and on a topsurface of the semiconductor substrate in the drain region next toanother side of the gate electrode, wherein while forming the siliconlayer, the silicon layer is formed by a selective epitaxial growthmethod so that the height of an upper end portion of the silicon layeras the drain region is higher than the height of an upper end portion ofthe silicon layer as the source region.

(15) In the fabrication method for a semiconductor device, according tothe above (14), it may be arranged such that while forming the siliconlayer, a selective epitaxial growth method is used to grow the siliconlayer whose thickness is controlled by controlling the size of a surfacearea of the semiconductor substrate where the silicon layer is grown.

(16) In the fabrication method for a semiconductor device, according tothe above (15), it may be arranged such that the size of the surfacearea for the silicon layer growth is controlled by changing the widthsof the source region and the drain region in the source-drain directionacross the gate electrode.

(17) In the fabrication method for a semiconductor device, according tothe above (14), it may be arranged such that the source region and thedrain region are formed such that the source region becomes wider thanthe drain region in the source-drain direction across the gateelectrode.

(18) In the fabrication method for a semiconductor device, according tothe above (14), it may be arranged such that: the gate electrode includemultiple and parallel gate electrodes; and the widths of the sourceregion and the drain region are controlled by changing a gap between thegate electrodes sandwiching the source region and a gap between thesource electrode sandwiching the drain region.

(19) In the fabrication method for a semiconductor device, according tothe above (14), it may be arranged such that the gap between the gateelectrodes sandwiching the source region is set so as to be wider thanthe gap between the gate electrodes sandwiching the drain region.

As explained above, according to the present invention, thenon-symmetricalness is applied to the structure of the source region andthe drain region, and the heights of the source region and the drainregion from a channel region differs; therefore, the electric fieldstrength in the vicinity of the source side and the vicinity of thedrain side can be changed on the end side of the gate. Thereby, thefield strength of the drain region side can be relaxed; and it ispossible to provide a semiconductor device which can suppress ageneration of a hot-carrier and thereby improving the hot-carriertolerance.

In addition, in a semiconductor memory device which employees astructure in which the non-symmetricalness is applied to the structureof the source region and the drain region, and in which the heights ofthe source region and the drain region from a channel region differs,the electric field strength in the vicinity of the source side and thevicinity of the drain side can be changed on the end side of the gate.Therefore, the electric field strength of the electrode on the sideconnected to the bit wiring and the electric field strength of theelectrode on the side connected to the capacitor can be different. As aresult, for example, by reducing the electric field strength applied onthe bit wiring, the problem of the signal delay of the wiring can beresolved; therefore, it is possible to realize a superior semiconductormemory device with refreshing performance without adding a specialphotolithography process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing the cross-sectional structure of asemiconductor device according to a first embodiment of the presentinvention.

FIG. 2 is a schematic diagram showing the planar structure of thesemiconductor device.

FIG. 3 is a cross-sectional schematic diagram explaining a fabricationmethod of the semiconductor device and shows a gate electrode formed ona semiconductor substrate.

FIG. 4 is a cross-sectional schematic diagram explaining the fabricationmethod of the semiconductor device and shows a silicon layer that hasbeen grown next to the gate electrode on a semiconductor substrate byselective epitaxial method.

FIG. 5 is a cross-sectional schematic diagram explaining the fabricationmethod of the semiconductor device and shows impurity doping.

FIG. 6 is a cross-sectional schematic diagram explaining the fabricationmethod of the semiconductor device and shows formed source and drainregions.

FIG. 7 is a cross-sectional schematic diagram explaining the fabricationmethod of the semiconductor device and shows formation of electrodelayers for external contact and in-between dielectric layers.

FIG. 8 is a top view showing an example where the shape of the gateelectrode has been changed in the semiconductor device.

FIG. 9 is a top view showing another example where the shape of the gateelectrode has been changed in the semiconductor device.

FIG. 10 is a cross-sectional schematic diagram explaining thefabrication method of the semiconductor memory device and shows as agate electrode is formed on a semiconductor substrate.

FIG. 11 is a cross-sectional schematic diagram explaining thefabrication method of the semiconductor device and shows as a siliconlayer has been grown next to the gate electrode on a semiconductorsubstrate.

FIG. 12 is a cross-sectional schematic diagram explaining thefabrication method of the semiconductor device and shows a formation ofthe source and drain regions by impurity doping.

FIG. 13 is a cross-sectional schematic diagram showing an example of thesemiconductor memory device according to the present invention.

FIG. 14 is a schematic diagram showing the planar structure of anexample of the semiconductor memory device.

FIG. 15 is a cross-sectional schematic diagram of the capacitorstructure portion of an example of the semiconductor memory device.

FIG. 16 is a diagram showing the relationship of: the space between thegates; and the thickness of the silicon layer (film thickness) grown byselective epitaxial method, which was obtained from experiments in theembodiments.

DETAILED DESCRIPTION OF THE INVENTION

Hereinbelow, a semiconductor device according to one embodiment of thepresent invention will be explained with reference to the drawings;however, the present invention is not limited only to the followingembodiments.

FIG. 1 is a schematic diagram showing a cross-sectional structure of afirst embodiment of a semiconductor device according to the presentinvention. In FIG. 1, a semiconductor substrate 1 applied to asemiconductor device H of the present invention is formed from, forexample, a semiconductor such as silicon, containing impurities of apredetermined density. A trench separation dielectric film (an elementseparation dielectric film) 2 is formed on a surface of thesemiconductor substrate 1 by an STI (Shallow Trench Isolation) method ina portion other than active regions K, and separates the adjacent activeregions K.

With the semiconductor device having the above aspect: in the regionwhere is sandwiched in-between the trench separation dielectric films 2,2 as shown in the cross-sectional structure of FIG. 1, a drain region 5and a source region 3 are separated and formed on the left and right; achannel region 6 is formed on a semiconductor substrate surface portionso as to be located in-between the source region 3 and the drain region5; a gate dielectric film 7 is formed and inserted between the sourceregion 3 and the drain region 5 on this channel region 6; and a gateelectrode 8 of the deposited structure is formed on this gate dielectricfilm 7. In addition, in FIG. 1, on the semiconductor substrate 1 at theright side of the gate electrode 8, a dummy gate electrode 9 where novoltage is applied to become the dummy, is formed next to the trenchseparation dielectric film 2 that is located on the right side. On thesemiconductor substrate 1, a dielectric film 10 is formed to cover thesource region 3, the drain region 5, and the gate electrode 8 and thedummy gate electrode 9, and furthermore a source electrode 12 thatconnects to the source region 3 and a drain electrode 13 that connectsto the drain region 5 are formed in a contact hole formed on thedielectric film 10, thus configuring a semiconductor device H. Thesource region 3 allows the bottom 3 a to reach the active region K ofthe semiconductor substrate 1, and that top 3 b is formed to extend outin an upward direction of the semiconductor substrate 1 at apredetermined thickness. In the thickness of this source region 3, thethickness (height) from the position of the top surface of semiconductorsubstrate 1 to the top surface of the source region 3 is denoted as t₁,while the thickness (height: total thickness) from the bottom of thesource region 3 reaching the active region K to the most upper end ofthe source region 3, which is projecting in an upward direction on thesemiconductor substrate, is denoted as t₂. In addition, the width of thesource region 3 in the cross-sectional structure in FIG. 1 is denoted asd₁.

The drain region 5 is formed such that: the bottom 5 a arrives at activeregion K of the semiconductor substrate 1; and the top of 5 b extendsout in an upward direction of the semiconductor substrate 1 at apredetermined thickness. In the thickness of this drain region 5, thethickness (height) from the position of the top surface of semiconductorsubstrate 1 to the top surface of the drain region 5 is denoted as t₃,while the thickness (height: total thickness) from the bottom of thedrain region 5 reaching the active region K to the most upper end of thedrain region 5 that is projecting in an upward direction on thesemiconductor substrate is denoted as t₄. In addition, the width of thedrain region 5 in the cross-sectional structure shown in FIG. 1 isdenoted as d₂.

The gate electrode 8 of the present embodiment has a laminated structureincluding an extending layer 15 consisting of a poly-silicon layer onthe gate dielectric film 7 located on the top surface of semiconductorsubstrate 1, a silicide layer 16 consisting of tungsten silicidelaminated on top of that, a metal layer 17 consisting of a tungstenlayer laminated on top of that, a hard dielectric film 18 laminated ontop of that, and side walls 20, 20 consisting of a silicon nitridingfilm to cover the growth layer 15, the silicide layer 16, the metallayer 17, and both sides of the hard dielectric film 18. In addition,like the gate electrode 8, the dummy gate electrode 9 where no voltageis applied, has a laminated structure including side walls 20, 20consisting of a silicon nitriding film to cover the growth layer 15, thesilicide layer 16, the metal layer 17, and both sides of the harddielectric film 18.

In the structure of the semiconductor device H, in the region where theright and left are sectioned from the element separation dielectricfilms 2, 2 as shown in FIG. 1, the width d₂ of the drain region 5 isformed so as to be narrower than the width d₁ of the source region 3; inother words, the width d₁ of the source region 3 is formed so as to bewider than the width d₂ of the drain region 5. Furthermore, the heightt₁ of the source region 3 formed to protrude out higher than the topsurface of semiconductor substrate 1 is formed so as to be lower thanthe height t₃ of the drain region 5 formed to protrude out higher thanthe top surface of semiconductor substrate 1; in other words, the heightt₃ of the drain region 5 is formed so as to be higher than the height t₁of the source region 3.

In addition, when explaining the source region 3 formed on thesemiconductor substrate 1, and the drain region 5 and the positionedinterval of gate electrodes 8 and 9, since the width d₂ of the drainregion 5 is narrower than the width d₁ of the source region 3, thedistance between the element separation dielectric film 2 on the leftside of FIG. 1 and the gate electrode 8 is formed so as to be longerthan the distance between gate electrodes 8 and 9.

In addition, the total layer thickness t₂ of the source region 3 and thetotal layer thickness t₄ of the drain region 5 are approximately thesame.

Incidentally, in reference to the configuration of the semiconductordevice H1 of FIG. 1, in recent MOS structures that are miniaturized, asone example, the width d₁ of the source region 3 located to the sides ofthe side wall 20 of the gate electrode 8 is formed to be substantially150 nm, the thickness t₁ of the source region 3 is formed to besubstantially 50 nm, the width d₂ of drain region 5 is formed to besubstantially 50 nm, and the t₃ is formed to be substantially 60 nm.

Next, the planar layout shape of the semiconductor device H of thecross-sectional structure can employ a layout structure in which: in theactive region K shown in for example FIG. 2, two sets of binarystructures where the source electrode 12 and the drain electrode 13 havebeen arranged to become a pair on the left and right side, are formed onone active region K; the gate electrode 8 is formed to extend across theactive region K so as to run along between the source electrode 12 andthe drain electrode 13 that have become paired on the left and right ina planar view; and the dummy gate electrode 9 is arranged beside thedrain electrode 13 that is roughly separated parallel to the gateelectrode 8.

In the layout structure shown in FIG. 2, other special wiring is notconnected to the dummy gate electrode 9, while the contact electrode 21for the gate supply is formed to the gate electrode 8 in an elementisolation region outside the active region K, and is configured so as tobe able to feed the gate electrode 8.

Next, an example of the process for producing the semiconductor deviceH1 of the structure shown in FIG. 1 and FIG. 2 will be explained basedon FIG. 3 to FIG. 7.

FIG. 3 is a diagram showing a cross-sectional structure after thesidewall structure of the gate electrode has been formed by a normal MOStransistor fabrication process.

In FIG. 3, the structure of the gate electrode is shown by referencenumeral 8, while the structure of the dummy gate electrode being thedummy is shown by reference numeral 9.

FIG. 4 shows the state after the selective epitaxial growth of thesilicon. The silicon layer formed by selective epitaxial growth on thesource region side is shown by reference numeral 30, while the siliconlayer formed by selective epitaxial growth on the drain region side isshown by reference numeral 31. In addition, for example, the width ofthe silicon substrate surface shown on the source region side is 150 nm,while the width of the silicon substrate surface shown in the drainregion side is 70 nm for example.

Next, it is clear from the test result of the later embodiment that thegrowth rate of the silicon at the time of the selective epitaxial growthhas a space-dependence between the gates. Under the deposition conditionin which: the flow rate ratio of dichlorosilane which constitutes thefilm growth atmosphere at the time of deposition and HCl is 200 to 100sccm; the deposition temperature is 800 degrees; and the vacuum degreein the deposition is 15 mTorr (2 Pa), it is possible to generate asilicon growth rate difference of about 20% between a portion where aspace between the gate electrode is with 70 nm, and a portion where aspace between the gate electrode is with 150 nm.

Thereby, it is possible to easily construct a transistor structure shownin FIG. 4 having a thickness construction in which a silicon layerthickness grown by selective epitaxial method is 50 nm in the sourceregion, while the thickness in the drain region is 60 nm.

Thereafter, as shown in FIG. 5, As (arsenic) is injected at a dose of4×10¹⁵ cm ⁻² over the entire surface at 30 keV. Next, the source region3 is formed on the source region side shown in FIG. 6 by activating theAs by heat-treating at 950° C. for 10 seconds; the drain region 5 isformed on the drain region side; and the MOS transistor structures wherethe depths in the silicon substrate of the impurities layers differ witheach other can be formed.

Next, if the dielectric film 36 is formed between layers, as shown inFIG. 7, and a contact hole is opened by normal photolithographytechnology and dry etching technology; and if a conductive film isaccumulated in the hole and the conductive film on the dielectric filmbetween layers is removed by CMP method, then the structure shown inFIG. 7 can be obtained, and this structure becomes equal with thestructure shown in FIG. 1.

If the semiconductor device H1 is of the structure shown in FIG. 1 orFIG. 7 that was provided by the fabrication method explained above, thenthe height t₃ of the drain region 5 that is higher than the channelregion can be raised higher than the height t₁ of source region 3, therelaxation of the electric field of the drain region 5 side can beacquired, and the MOS transistor which is superior in hot-carriertolerance can be provided.

Incidentally, the planar layout structure of the transistor used for thepresent invention is not limited only to the case having a dummy gateelectrode 9 shown in FIG. 2. And even when the gate electrode 37 is bentso as to be the U-shape in a planar view as shown in FIG. 8, to surroundthe drain region 5, the similar effect can be obtained. In addition, asshown in FIG. 9, even when the structure where the gate electrode 38 isarranged so as to surround the region of the drain region 5, the similareffect can be obtained.

Next, an example of applying the semiconductor device structureaccording to the present invention to a semiconductor memory device(DRAM) will be explained with reference to FIG. 10 to FIG. 15.

FIG. 10 to FIG. 13 are diagrams to explain the fabrication process ofthe semiconductor memory device according to the present invention stepby step, and the semiconductor memory device of the structure shown inFIG. 13 to FIG. 15 is provided. In addition, FIG. 15 is an example ofthe capacitor structure arranged three-dimensionally in the upperportion of the semiconductor device and the bit wiring and the wordwiring shown in FIG. 13 and FIG. 14 in a deposited form.

With this embodiment, an example structure for when the presentinvention is applied to the cell structure having a memory cell of 2bits is arranged in one active region K is shown.

With the structure of this embodiment, as shown in the planar structurein FIG. 14, the plurality of elongated strip active regions K1 areformed so as to be arranged at predetermined intervals individually; theimpurities diffusion layers are individually arranged in both ends andthe central part of each active region K1. Furthermore, in this form,the drain region 43 is formed in the central region; the source regions44 and 45 are formed in both ends side; and the contact region (sourceelectrode) 46, the contact region (drain electrode) 47, and the contactregion (drain electrode) 48 are specified so as to be just above them inan arranged form.

In addition, the active region K1 of the planar shape such as shown inthe above-mentioned diagram in the present embodiment has a specificshape, but since the shape and the direction of the active region K1should not be especially limited, the shape of the active region K1shown in FIG. 14 may of course employ other active region shapes whichis applicable to transistors of general semiconductor memory devices,and is not limited to the shape of the present embodiment.

Next, bit wirings 50 are extended in the widthwise (X) direction of FIG.14 in the shape of a polygonal line. In addition, linear word wirings 51and dummy word wirings 52 extending along the lengthwise (Y) directionof FIG. 14 are arranged at predetermined intervals along the widthwise(X) direction of FIG. 1. The word lines 51 are configured so as toinclude the gate electrode 8 or the dummy gate electrode 9 at portionsintersecting with the active region K1.

Also in the transistor structure of the semiconductor memory device ofthe present embodiment, like the semiconductor device H1 that wasexplained in the above with reference to FIG. 1, the gate electrode 8 orthe gate electrode 9 is arranged in an activate region K1 sectionedbetween the element separation dielectric films 2, 2. In the presentembodiment, the dummy gate electrode 9 on the element separationdielectric film 2 on the left, the gate electrodes 8, 8 having astructure capable of feeding, and the dummy gate electrode 9 on elementseparation dielectric film 2 on the right side, are arranged in orderfrom the left of FIG. 1. In the DRAM structure, since the elementseparation dielectric film 2 and the activated region K1 are arranged inplural numbers repeatedly, and thereby forming the planar structureshown in FIG. 14.

Since the structure of the gate electrodes 8, 9 and the structure of thesemiconductor substrate 1 are basically equivalent to the structure ofsemiconductor device H1 that was shown in FIG. 1, explanation thereforwill be omitted here.

In the present embodiment, one source region 3 is established in thecentral part of activated region K1, and drain regions 5, 5 areseparately arranged on both the left and right sides. Therefore, thechannel region and the drain regions 5, 5 are formed on both the leftand right sides of source region 3.

The relationship of the thickness of these source regions 3 and therelationship of the thickness of the drain region 5 are basicallyequivalent to the structure shown in FIG. 1.

In addition, in the contact regions 46, 47, and 48 shown in FIG. 15, acapacitor structure showing a cross-sectional structure in FIG. 15 isformed as an example. In the structure according to the present example:a second in-between dielectric film 60 is formed on a dielectric film 10shown in FIG. 13; contact holes 61, 62, and 63 are formed individuallyat the corresponding positions on contact portions 46, 47, and 48 in thesecond in-between dielectric film 60; contact plugs 64, 65, and 66 areformed in these contact holes; and a bit wiring 50 is arranged on thecontact plug 65. Furthermore, a third in-between dielectric film 67 isformed on the second in-between dielectric film 60; a fourth in-betweendielectric film 68 is formed on the third in-between dielectric film 67;a capacity memory portion 73 including a lower electrode 70, a capacitydielectric film 71, and an upper electrode 72 are formed so as to befilled in a cylinder hole 69 formed in the fourth in-between dielectricfilm 68; and each of the capacity memory portions 73 is connected to acontact region (source electrode) 46 or a contact region (drainelectrode) 48, shown in FIG. 13, and the DRAM structure is therebyconfigured.

In the DRAM structure configured as above, the height of the top of thedrain region 5 from the channel region being a reference, is formed soas to be higher than the height from the channel region to the top ofsource region 3 that is located in the upper portion than the channelregion.

Other structures are basically similar to the structure of previouslymentioned semiconductor device H1 in FIG. 1.

In the DRAM planar layout structure diagram shown in FIG. 14, the spaceE which is the space between the gates that forms a contact portion 46for the bit wiring is a wider layout than the space F between the gatesthat form a contact portion 47 and 48 for capacitors. In this case, forexample, the space E can be 70 nm and the space F can be 50 nm.

To obtain the structure shown in FIG. 13, after having formed the sidewall structure of the pass gate of the memory cell as shown in FIG. 10using a normal DRAM fabrication process, the following process isperformed.

As clear from test results mentioned later, the growth rate of theselective epitaxial growth silicon depends on the space between thegates, and when the conditions of the flow rate ratio is 200 to 100 sccmfor the dichlorosilane and HCL, the deposition temperature is 800degrees, and the vacuum degree at the time of deposition is 15 mTorr,the growth rate difference of 5% occurs between the 50 nm portion andthe 70 nm portion in the space between the gates.

Thereby, it is possible to fabricate a transistor configuration inwhich: the thickness of the silicon film 80 a formed by selectiveepitaxial method is 60 nm at the space portion 80 between the gates thatforms a contact for the bit wiring; and the silicon films 81 a and 82 aare 63 nm at spaces 81 and 82 between the gates that form the contactfor capacitors.

After this, P (phosphorus) is injected over the entire surface at 1×10¹³cm⁻² and 60 keV. Thereby, it is possible to form the MOS transistorhaving a source region 80 b and drain regions 81 b and 82 b, where thedepth in the silicon substrate of the impurities layer differ at theregions where contacts for bit wires and for capacitors shown in FIG. 11are formed.

Next, an in-between dielectric film is formed; contact holes are openedby normal lithography technology and dry etching technology; afteraccumulating conductive films 46, 47, and 48 in the hole simultaneously,the conductive films are removed from the in-between dielectric filmlayer by the CMP method; and heat-treatment at 980° C. for 10 seconds,and thereby forming the structure shown in FIG. 13. With this structure,a DRAM can be obtained which has superior refreshing performance byrelaxing an electric field of the capacitor contact side.

For example, in the above-mentioned structure, in the space between thegates of the cell contact side and the bit wiring contact side in a DRAMtransfer MOS transistor, the space between the gates of the cell contactside is formed so as to be narrower than the bit line contact side.

As a result, since the selective epitaxial growth rate of the cellcontact side can be grown faster than the speed of the selectiveepitaxial growth of the bit line contact side, the film thickness of thesilicon by the selective epitaxial of the cell contact side is formed soas to be thicker than the film thickness of the silicon of the bit linecontact side.

And, by thereafter introducing the impurities for the source/drains, theimpurities density distribution of the source side and the drain sidecan be non-symmetricalness. That is to say, the DRAM having the superiorrefreshing performance can be formed by relaxing the electric field ofthe cell contact side (drain electrodes 5, 5 side). In addition, sinceit is not necessary to add a lithography process for the injection inthe process of forming the non-symmetricalness in the impurities densitydistribution, the process can be carried out easily.

EMBODIMENT Test Examples

After the element separation dielectric film is formed on the siliconsubstrate by an STI method, a photolithography method is performedrepeatedly, and thereby forming a gate electrode and a dummy gateelectrode having the structure shown in FIG. 3.

In the structure shown in FIG. 3, in order to apply the followingselective epitaxial method, each sample was formed such that: the widthof the semiconductor substrate located to the sides of the side wall ofthe gate electrode was 150 nm; the intervals of the gate electrode andthe dummy gate electrode are set to be 50 nm, (110) nm, 260 nm, 270 nm,280 nm, and 520 nm (the range within 50 nm to 520 nm).

Here, following selective epitaxial method, when a deposition conditionis made such that: the flow rate ratio between the dichlorosilane andHCl is 200 to 100 sccm; the deposition temperature is 800 degrees; andthe vacuum degree in the deposition is 15 mTorr (2 Pa), it wasrecognized that the state where the silicon layer grows on the siliconsubstrate can be indicated by the correlation shown in FIG. 16.

From the correlation shown in FIG. 16, it is understood that the growthrate difference of about 20% is generated in the space between the gateelectrodes with the 70 nm portion and 150 nm portion.

It became clear that when a silicon film is grown in this manner byusing selective epitaxial method, the film thickness of the providedsilicon film could be controlled by regulating the space between thegate electrodes.

Embodiment 1

In order to produce the structure shown in FIG. 1, a gate electrodehaving the sidewall structure shown in FIG. 3 was formed according tothe MOS transistor fabrication process. The width of the siliconsubstrate surface shown on the source side was 150 nm and the width ofthe silicon substrate surface shown on the drain side was 70 nm.

An Si board is employed as the semiconductor substrate, and the gateelectrode having a 70 nm thick poly-silicon extending layer, a 5 nm to10 nm thick tungsten silicide layer, a 50 nm thick tungsten metal layer,a 140 nm thick silicon nitride hard dielectric film, and a 20 nm thickside wall was formed at the intervals as previously mentioned.

Next, a silicon layer was grown by the selective epitaxial method with acondition of: the flow rate ratio between the dichlorosilane and HCl of200 to 100 sccm; the deposition temperature of 800 degrees; and thevacuum degree in the deposition of 15 mTorr (2 Pa). As the result, agrowth rate difference of about 20% was generated in the space betweenthe gate electrodes at the 70 nm portion and 150 nm portion, and atransistor structure was formed where the silicon film thickness was 50nm at the source region and 60 nm at the drain region. Thereafter, As(arsenic) was injected over the entire surface of the semiconductorsubstrate at 4×10¹⁵ cm⁻² and 30 keV.

Next, by activating the As by heat-treatment at 950° C. for 10 seconds,an MOS transistor was made where the depth in the silicon substrate ofthe impurities layer in the source and the drain regions shown in FIG. 4differs.

Embodiment 2

In order to produce a DRAM having the layout structure shown in FIG. 13to FIG. 14, a gate electrode including the sidewall structure shown inFIG. 13 is formed following an MOS transistor fabrication process. Inthe planar layout structure shown in FIG. 14, space E was 70 nm, andspace F was 50 nm.

An Si board is employed as the semiconductor substrate, and the gateelectrode including a 70 nm thick poly-silicon extending layer, a 5 nmto 10 nm thick tungsten silicide layer, a 50 nm thick tungsten metallayer, a 140 nm thick silicon nitride hard dielectric film, and a 20 nmthick side wall, were formed at the intervals previously mentioned.

Next, a silicon layer was grown by selective epitaxial method under thecondition of: the flow rate ratio between the dichlorosilane and HCl of200 to 100 sccm; the deposition temperature of 800 degrees; and thevacuum degree in the deposition of 15 mTorr (2 Pa). As the result, atthe portion where the space between the gate electrode of the bit wiringcontact side is 70 nm, and at the portion where the space between thegate electrode of the capacitor contact side is 50 nm, a growth ratedifference of 5% occurred, and thereby forming a structure where thethickness on the space side between the gate electrode of the bit wiringcontact side was 60 nm, and on the space side between the gate electrodeof the capacitor contact side the thickness was 63 nm.

Thereafter, P (phosphorus) is injected over the entire surface of thesemiconductor at 1×10¹³ cm⁻² and 60 keV.

Thereby, an MOS transistor could be made, in which the depths in thesilicon substrate of the impurities layer differ at the regions wherecontacts for bit wires and for capacitors shown in FIG. 13 are formed.Next, the structure shown in FIG. 13 was made by: forming an in-betweendielectric film of silicon nitride; opening contact holes by thelithography technology and the dry etching technology; afteraccumulating the conductive films in the hole simultaneously, removingthe conductive films on the in-between dielectric film; and performing aheat-treatment at 980° C. for 10 seconds.

While preferred embodiments of the invention have been described andillustrated above, it should be understood that these are an exemplaryof the invention and are not to be considered as limiting. Additions,omissions, substitutions, and other modifications can be made withoutdeparting from the spirit or scope of the present invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description, and is only limited by the scope of theappended claims.

1. A semiconductor device comprising: a substrate; an isolation regionselectively formed in the substrate to define an active region; a gateelectrode passing over the active region; a first region formed in theactive region with a first peripheral edge defined by the isolationregion and a second peripheral edge defined by the gate electrode, thefirst region having an upper surface; a first silicon layer formed onthe upper surface of the first region; a dummy gate electrode passingover the active region; a second region formed in the active region witha third peripheral edge defined by the isolation region, a fourthperipheral edge defined by the gate electrode and a fifth peripheraledge defined by the dummy gate electrode, the second region having anupper surface that is different in area from the upper surface of thefirst region; and a second silicon layer formed on the upper surface ofthe second region, the second silicon layer being different in thicknessfrom the first silicon layer.
 2. The semiconductor device according toclaim 1, wherein the thickness of the first silicon layer is smallerthan the second silicon layer thereof.
 3. The semiconductor deviceaccording to claim 1, wherein the area of the upper surface of the firstregion is larger than the upper surface of the second region thereof. 4.The semiconductor device according to claim 1, wherein no voltage isapplied to the dummy gate.
 5. The semiconductor device according toclaim 1, wherein each of the first and second silicon layers isepitaxial growth layer that is the substantially same as a crystalstructure of the active region.
 6. The semiconductor device according toclaim 1, further comprising: a bit wiring connected to the first siliconlayer; and a capacitor connected to the second silicon layer.
 7. Asemiconductor device comprising: a semiconductor substrate; an isolationregion selectively formed in the semiconductor substrate to define anactive region, the active region having an upper surface; first andsecond gate lines each crossing over the active region to divide theupper surface of the active region into first, second and third surfaceportions, the first surface portion being between the first and secondgate lines, the second surface portion being between the first gate lineand the isolation region, and the third surface portion being betweenthe second gate line and the isolation region; a third gate linecrossing over a part of the second surface portion so that a remainingportion of the second surface portion between the first and third gatelines is smaller in width than the first surface portion; and first andsecond silicon layers formed on the first surface portion and theremaining portion of the second surface portion, respectively, the firstand second silicon layers being different in thickness from each other.8. The semiconductor device according to claim 7, further comprising afourth gate line crossing over a part of the third surface portion sothat a remaining portion of the third surface portion between the secondand fourth gate lines is smaller in width than the first surfaceportion, and a third silicon layer formed on remaining portion of thethird surface portion, respectively, the first and third silicon layersbeing different in thickness from each other.
 9. The semiconductordevice as claimed in claim 8, wherein the first silicon layer is smallerin thickness than each of the second and third silicon layers.
 10. Thesemiconductor device according to claim 7, wherein the first siliconlayer is smaller in thickness than each of the second silicon layers.11. The semiconductor device according to claim 7, wherein no voltage isapplied to the third gate line.
 12. The semiconductor device accordingto claim 7, wherein each of the first and second silicon layers isepitaxial growth layer that is the substantially same as a crystalstructure of the active region.
 13. The semiconductor device accordingto claim 7, further comprising a bit wiring connected to the firstsilicon layer, and a capacitor connected to the second silicon layer.14. A semiconductor device comprising: a semiconductor substrate; anisolation region selectively formed in the semiconductor substrate todefine an active region, the active region including first, second andthird surface portions arranged in line in a first direction, the firstsurface portion being between the isolation region and the secondsurface region, and the second surface region being between the firstand third surface portions; a first gate structure elongated in a seconddirection, that intersects the first direction, to cross over the secondsurface portion of the active region; a second gate structure elongatedin the second direction to cross over a part of the first surfaceportion of the active region, the second gate structure expanding in thefirst direction to cover a part of the isolation region, a remainingpart of the first surface portion being defined between the first andsecond gate structures, the remaining part of the first surface portionbeing smaller in width than the third surface portion; a first siliconlayer formed in contact with the remaining part of the first surfaceportion of the active region; and a second silicon layer formed incontact with the third surface portion of the active region, the secondsilicon layer being different in thickness from the first silicon layer.15. The semiconductor device according to claim 14, wherein the activeregion further includes a fourth surface portion, the third surfaceportion being between the second and fourth surface portions, and thesemiconductor device further comprises a third gate structure elongatedin the second direction to cross over the fourth surface portion of theactive region.
 16. The semiconductor device according to claim 14,wherein the first silicon layer is greater in thickness than each of thesecond silicon layers.
 17. The semiconductor device according to claim14, wherein no voltage is applied to the second gate structure.
 18. Thesemiconductor device according to claim 14, wherein each of the firstand second silicon layers is epitaxial growth layer that is thesubstantially same as a crystal structure of the active region.
 19. Thesemiconductor device according to claim 14, further comprising a bitwiring connected to the first silicon layer, and a capacitor connectedto the second silicon layer.
 20. The semiconductor device according toclaim 14, wherein each of the first and second gate structure includes agate insulator, a gate electrode and a spacer insulating film coveringthe gate electrode.